1. Field
Exemplary embodiments of the present invention relate to an integrated circuit design, and more particularly, to a double data rate (DDR) counter, an analog-digital converter, and a CMOS image sensor using the same.
2. Description of the Related Art
In general, an analog-digital converter (ADC) may be used for various electronic devices to convert a valid physical parameter, such as intensity of light, intensity of sound, or time, into a digital signal.
For example, an image sensor acquires an image by using the properties of semiconductor responding to incident light, and includes an analog-digital converter to convert an analog signal outputted from a pixel array into a digital signal. The analog-digital converter includes a counter to perform a counting operation using a clock.
Meanwhile, the operating speed and power consumption of the counter have a direct effect on the performance of a device or system including the counter. In particular, a CMOS image sensor may include a plurality of counters to convert analog signals, which are outputted in the unit of column from an active pixel sensor array, into digital signals. The number of counters may be increased depending on the resolution of the CMOS image sensor. As the number of counters increases, the operating speed and power consumption of the counter may serve as an important factor to determine the entire performance of the image sensor.
Thus, a double data rate (DDR) counter is proposed to reduce the power consumption in a CMOS image sensor using a single-slope ADC. The DDR counter may realize the same resolution while reducing counter speed to the half. Furthermore, the DDR counter may apply a digital double sampling (DDS) technique to remove an offset by using output codes of a reset voltage and a signal voltage, respectively.
However, in order to implement the conventional DDR counter, the number of peripheral circuits, such as flip-flops and multiplexers, may increases. With the increase in number of the peripheral circuits, circuit complexity inevitably increases. As a result, the power consumption of the counter may be increased, and the operating speed of the counter may be reduced.